When data is to be stored in a DRAM, it is typically captured in latches where it is temporarily stored while the bit lines which are to receive the data prior to storage in storage cell capacitors are precharged. In modern DRSMs, it is desirable to minimize the current drawn, and one of the sources of wasted current is in the latches.
CMOS circuits which have inputs compatible with other logic families, such as TTL, may consume significant static power while inputs remain at static logic levels. In the TTL case, logic "1" inputs can be as low as 2.4 volts, while in a 5 volt CMOS part the input is typically positioned mid-voltage rail, resulting in wasted current.
The standby current in a DRAM is significant because many chips are typically needed for large memory banks. For example, a 4 Mb DRAM has 11 address inputs and several other inputs which must be latched at the start of a memory cycle. Instead of using static latches, DRAM circuits typically make use of dynamic latches in which current can only flow during the actual latching sequence.
Such a circuit is shown in FIG. 1, which is a schematic diagram of a dynamic latch circuit in accordance with the prior art. This circuit is shown in an article by Miyamoto et al in IEEE Journal of Solid State Circuits, 4/90.
A flip flop 1 is used to store a bit and present it to output inverters 3 and 5 for provision to output leads/Ai and Ai. Field effect transistors (FETs) 6 and 7, which have their source-drain circuits in parallel with the output FETs of flip flop 1 are driven from a clock source RA1. Two circuits 8 and 9 each comprised of a series of three FETs are connected respectively between the outputs of flip flop 1 and ground. Two opposite FETs of the both series circuits have a clock source/RA3 applied to their gates, and two opposite FETs of both series circuits have a clock source RA1 applied to their gates. A data input terminal receives data pulses and applies them to the gate of a third FET 11 in one of the series circuits. The gate of the third FET 13 of the other series circuit is connected to a voltage reference.
A clock signal/RA2 is applied to the common terminal of the flip flop 1.
FIG. 1A is a timing diagram of the clock signals RA1, /RA2 and /RA3, which are derived from a master clock signal /RAS. When the input FET 11 conducts due to the presence of a high logic level input data signal, it is compared with the current in a matched reference FET which is preferably set between minimum and maximum TTL input logic levels, the reference level being exhibited as a reference voltage Vref at the gate of FET 13. When the input data exceeds the reference in one polarity direction, the flip flop stores an input data pulse of one polarity, and when it exceeds the reference in the other polarity direction, the flip flop stores an input data pulse of the other polarity.
A reference voltage generator is shown in FIG. 1B. A pair of complementary FETs 15 and 16 have their source-drain circuits connected in series, between a current source I and ground. The gates and drains of both transistors are connected together.
While the latch itself consumes virtually zero static power, the reference voltage generator does consume standby power. In addition, it cannot be used in an SRAM, because it is necessary to synchronize data and clock prior to presentation of the data to the latch, while in an SRAM there is no certainty of whether the data will precede or be later than the clock.
Synchronous DRAMs can utilize different CAS latency modes of operation. For example, for a CAS latency of 1, data which is read by its data bus read amplifier arrives at its output buffer after the clock. For a CAS latency of 3, the data waits for the clock at a stage preceding the output buffer. For a latency of 2 there is a race condition between the data and the clock to the output buffer.
A description of SDRAMs may be found in the article "Synchronous DRAMs: Designing to the JEDEC Standard", in MICRON Design Line, volume 2, Issue 2, No 2Q93.